Accumulator-based built-in self-test generator for robustly detectable sequential fault testing
In this paper an algorithm for the generation of single input change (SIC) pairs is presented, termed the accumulator-based SIC pair generation (ASG) algorithm; SIC pairs have been effectively utilised for testing robustly detectable sequential faults. ASG is implemented in hardware utilising an accumulator whose inputs are driven by a barrel shifter. Since such structures (accumulators whose inputs are driven by barrel shifters) are commonly found in current, high-speed signal processing VLSI circuits, the presented schema provides a practical solution for the built-in testing of such circuits for testing delay and stuck-open faults. Utilisation of ASG to applying SIC pairs to adjacent pairs of inputs of the CUT, resulting in pseudoexhaustive schemes, is also addressed.