Efficient Test Generation for Register Transfer Level Descriptions
Test generation based on high level circuit descriptions, has been proposed in the recent years, for LSI and VLSI products. However, not all aspects of the problem have been thoroughly examined. This paper describes an efficient approach, aiming to the reduction of the computation time and input assignment requirements per test pattern. Our methodology is based on a new mode for propagating the fault symptoms through high level primitives, namely the assignments free propagation, along with a number of techniques that support this mode of propagation. Another advantage of our methodology is that it can be adapted to different algorithms. First practical results demonstrate the feasibility of our approach.