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Optimal Periodic Testing of Intermittent Faults In Embedded Pipelined Processor Applications

dc.contributor.authorKranitis, N.
dc.contributor.authorMerentitis, A.
dc.contributor.authorLaoutaris, N.
dc.contributor.authorTheodorou, G.
dc.contributor.authorPaschalis, A.
dc.contributor.authorGizopoulos, D.
dc.contributor.authorHalatsis, Constantin
dc.description.abstractToday's nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability failures that are manifested in the field during the semiconductor product operation. Since software-based self-test (SBST) has been proposed as an effective strategy for on-line testing of processors integrated in non-safety critical low-cost embedded system applications, optimal test period specification is becoming increasingly challenging. In this paper we first introduce a reliability analysis for optimal periodic testing of intermittent faults that minimizes the test cost incurred based on a two-state Markov model for the probabilistic modeling of intermittent faults. Then, we present for the first time an enhanced SBST strategy for on-line testing of complex pipelined embedded processors. Finally, we demonstrate the effectiveness of the proposed optimal periodic SBST strategy by applying it to a fully-pipelined RISC embedded processor and providing experimental resultsen_UK
dc.publisherIEEE Xploreen_UK
dc.relation.ispartofseriesDesign, Automation and Test in Europe, 2006. DATE '06. Proceedings;Volume:1
dc.rights© 2006 EDAAen_UK
dc.subjectResearch Subject Categories::TECHNOLOGYen_UK
dc.subjectOptimal Periodic Testingen_UK
dc.titleOptimal Periodic Testing of Intermittent Faults In Embedded Pipelined Processor Applicationsen_UK
dc.typeWorking Paperen_UK

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© 2006 EDAA
Except where otherwise noted, this item's license is described as © 2006 EDAA