Hierarchical robust test generation for CMOS circuit stuck-open faults
As VLSI circuits become very large the complexity of test derivation becomes tremendous. The performance of test derivation can be improved significantly by exploiting the hierarchical structure found in most realistic circuits and supported by current computer-aided design systems. In this direction, a new hierarchical test generation methodology for transistor stuck-open (TSOP) faults in combinational CMOS circuits, is presented. The contribution of this work is twofold. For the designer of the CMOS cells we give a method, based on the Karnaugh map, to generate the sufficient test information for the CMOS cells, and for the designer of a VLSI circuit consisting of these CMOS cells we give a method to generate robust two-pattern tests for the whole VLSI circuit exploiting the test information given for any one of the used CMOS cells.