On robust two-pattern testing of one-dimensional CMOS iterative logic arrays

Gizopoulos, Dimitris ; Paschalis, Antonis ; Nikolos, Dimitris ; Halatsis, Constantin (1999)

Article

In this paper a graph model and a method to construct robust (for the first time in open literature) as well as non-robust two-pattern tests for one-dimensional iterative logic arrays (ILAs) are presented. Exploring the graph structure we can find two-pattern tests that can be applied with a constant or linear number of test vectors to all the ILA cells. Such tests are subsequently characterized as robust or non-robust two-pattern tests

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c 1999 Taylor & Francis Ltd.
Except where otherwise noted, this item's license is described as c 1999 Taylor & Francis Ltd.