Analysis of a Modified Model for Synchronous Multiprocessor Systems
The paper presents an analysis of a modified model for synchronous multiprocessor systems. In this model, besides the shared memory modules, each processor has a private memory. The memory references of each processor are not uniformly distributed among the memory modules, and the rates of request for interconnection varies between 0 and 1 per memory cycle. The interconnection network is considered to be either a crossbar or a shared bus. The performance analysis uses as performance metrics the bandwidth (BW) processor utilization (U) and the memory request completion time (D). Relations among them are derived.